Vertical air gap subtractive etch back end metal

A method of forming a semiconductor structure comprising:

• forming source/drain regions on opposite sides of a gate structure located over a channel region of a semiconductor material layer;
• forming source/drain contact structures in an interlevel dielectric (ILD) layer overlying the semiconductor material layer, each of the source/drain contact structures contacting one of the source/drain regions;
• recessing the ILD layer to expose an upper portion of each of the source/drain contact structures;
• forming a sacrificial layer over a remaining portion of the ILD layer to laterally surround the upper portion of each of the source/drain contact structures;
• forming an interconnect conductor portion over the sacrificial layer to contact at least one of the source/drain contact structures;
• removing the sacrificial layer to re-expose the upper portion of each of the source/drain contact structures;
• and
• forming an interconnect liner portion, the interconnect liner portion having a first portion present on top and sidewall surfaces of the interconnect conductor portion and a second portion enclosing an air gap located between the interconnect conductor portion and the remaining portion of the ILD layer.