Timing/power risk optimized selective voltage binning using non-linear voltage slope

A method, comprising:

• manufacturing integrated circuit devices according to an integrated circuit design using manufacturing equipment, the integrated circuit design producing integrated circuit devices that are identically designed and perform at different operating speeds caused by manufacturing process variations;
• determining the minimum operating voltage and hardware variations for each device in the integrated circuit design and dividing a process distribution for the integrated circuit devices into process windows;
• for each integrated circuit device in each of the process windows, establishing bin-specific voltage limits for each supply voltage based on the integrated circuit design for each process window, the bin-specific voltage limits being a maximum voltage (Vmax) and minimum voltage (Vmin) to support performance at system frequency (Fsys) for the integrated circuit device in each process window;
• identifying all the devices on each integrated circuit devices and calculating Vmin vs. process-bin mean and sigma sensitivity using information about specific integrated circuit devices;
• identifying voltages for each process window that generates Vmin for the specific integrated circuit devices, Vmin being a minimum voltage needed for functionality of each element at design maximum and minimum operating speeds for the integrated circuit device;
• evaluating power at the slow end and fast end of each process window using the voltage necessary to support the system frequency (Fsys) and determining highest power (Pmax);
• determining the maximum voltage (Vmax) for each process window that generates the highest power (Pmax);
• and
• identifying a voltage between Vmin and Vmax that maximizes timing margin for system frequency (Fsys) while minimizing risk for the highest power (Pmax).

A system, comprising:

• a processor;
• a tester operatively connected to the processor;
• and
• a performance monitor operatively connected to the processor,
• the processor determining the minimum operating voltage and hardware variations for each device in an integrated circuit design and dividing a process distribution for chips manufactured from an identical circuit design into process windows, using the performance monitor,
• the processor establishing bin-specific voltage limits for each supply voltage based on the integrated circuit design for each process window, the bin-specific voltage limits being a maximum voltage (Vmax) and minimum voltage (Vmin) to support performance at system frequency (Fsys) for the integrated circuit device in each process window,
• the tester identifying all the devices on each chip and verifying that Vmin requirements for each assigned bin are met,
• the processor identifying the voltages for each process window that generates Vmin for specific integrated circuit devices, Vmin being a minimum voltage needed for functionality of each element at design maximum and minimum operating speeds for the integrated circuit device,
• the processor evaluating power at the slow end and fast end of each process window using the voltage necessary to support the system frequency (Fsys) and determining highest power (Pmax), using the performance monitor,
• the processor determining the maximum voltage (Vmax) for each process window that generates the highest power (Pmax),
• the processor identifying a voltage between Vmin and Vmax that maximizes timing margin for system frequency (Fsys) while minimizing risk for the highest power (Pmax), and
• the processor sorting the chips into different process windows using the tester, based on the voltage identified between Vmin and Vmax, each of the process windows having a bin-specific voltage limit such that the bin-specific voltage limit for all integrated circuit devices in a given process windows is set consistent with application conditions for the integrated circuit devices.