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US 2017/0287565 A1Published application
Apparatuses and methods using dummy cells programmed to different states
AssigneeMicron Technology, Inc.
InventorsToru Tanzawa, Aaron Yip
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.
Claims20
An apparatus, comprising:
- a first vertical memory string including a first plurality of memory cells;
- a second vertical memory string including a second plurality of memory cells;
- and
- a control unit configured to provide control signals to activate the first plurality of memory cells of the first vertical memory string and to further deactivate at least one of the second plurality of memory cells of the second vertical memory string.
1 more element
An apparatus comprising:
- a first plurality of vertically-oriented cells respectively coupled to a bit line of a first set of adjacent bit lines and a word line, the first plurality of vertically-oriented cells having a first target threshold voltage;
- and
- a second plurality of vertically-oriented cells respectively coupled to a bit line of a second set of adjacent bit lines and the word line, the second plurality of vertically-oriented cells having a second target threshold voltage,
- wherein a control signal provided to the word line is configured to activate the first plurality of vertically oriented cells and to deactivate the second plurality of vertically-oriented cells.
1 more element
A method comprising:
- providing a control signal to a plurality of vertical memory cells respectively coupled to adjacent bit lines;
- activating a first set of memory cells of the plurality of vertical memory cells coupled to a first set of alternating bit lines of the adjacent bit lines, responsive to the control signal;
- and
- deactivating a second set of memory cells of the plurality of vertical memory cells coupled to a second set of alternating bit lines of the adjacent bit lines, responsive to the control signal.
1 more element
Dependencies are inferred from the claim text.