Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell

A leakage-aware activation control circuit for controlling activation of a delayed keeper circuit in a dynamic read circuit for a memory bit cell, comprising:

• means for providing an N-type Field-Effect Transistor (NFET) leakage indicator indicating leakage current of at least one NFET in a dynamic read circuit;
• means for providing a P-type FET (PFET) leakage indicator indicating leakage current of at least one PFET in the dynamic read circuit;
• means for receiving the NFET leakage indicator and the PFET leakage indicator;
• means for comparing the NFET leakage indicator to the PFET leakage indicator;
• means for generating a FET leakage signal based on the comparison of the NFET leakage indicator to the PFET leakage indicator;
• and
• means for adaptively generating at least one control signal based on the FET leakage signal to control activation timing of a delayed keeper circuit.

A memory system, comprising:

• a memory bit cell comprising:
• a storage circuit configured to store a complement voltage;
• and
• a read port circuit coupled to the storage circuit, the read port circuit configured to generate the complement voltage on a dynamic node in response to a read operation;, p;
• a dynamic read circuit, comprising:
• the dynamic node;
• a delayed keeper circuit configured to be activated in response to a pulse to keep the complement voltage on the dynamic node outside of an evaluation phase, and configured to be deactivated in response to the pulse in response to the evaluation phase of the read operation;
• a leakage-aware activation control circuit, comprising:
• a leakage circuit configured to generate a FET leakage signal based on a comparison of leakage current of at least one N-type FET (NFET) to leakage current of at least one P-type FET (PFET);
• and
• a control signal generator configured to adaptively generate at least one control signal based on the FET leakage signal to control activation timing of a second delayed keeper circuit;
• and
• a pulse generator configured to generate the pulse having a pulse width based on a control activation timing for activation and deactivation of the second delayed keeper circuit in response to the at least one control signal.