Semiconductor device

An apparatus comprising:

• a plurality of word lines having mutually different allocated addresses;
• an address output circuit configured to provide the address;
• a row decoder configured to access any of the plurality of word lines indicated by the address in response to a first control signal;
• a first latch circuit configured to latch the address in response to a second control signal different from the first control signal;
• a first comparator circuit configured to compare the address output from the address output circuit and the address latched by the first latch circuit in response to the second control signal, and
• wherein the second control signal is less frequently activated than the first control signal.

An apparatus comprising:

• a plurality of word lines having mutually different allocated addresses;
• an address output circuit configured to provide the address;
• a row decoder configured to access any of the plurality of word lines indicated by the address in response to a first control signal;
• a first latch circuit configured to latch the address in response to a second control signal different from the first control signal;
• a first comparator circuit configured to compare the address output from the address output circuit and the address latched by the first latch circuit in response to the second control signal;
• and
• an address scrambler configured to generate an additional address related to and different from the address latched by the first latch circuit in response to activation of a third control signal when the address from the address output circuit and the address latched by the first latch circuit match.

An apparatus comprising:

• a plurality of word lines having mutually different allocated addresses;
• an address output circuit configured to provide the address;
• a row decoder configured to access any of the plurality of word lines indicated by the address in response to a first control signal;
• a first latch circuit configured to latch the address in response to a second control signal different from the first control signal;
• a first comparator circuit configured to compare the address output from the address output circuit and the address latched by the first latch circuit in response to the second control signal;
• a second latch circuit configured to latch the address output from the address output circuit in response to activation of the third control signal;
• and
• a second comparator circuit configured to compare the address from the address output circuit and the address latched by the second latch circuit in response to the third control signal.