Timing control for unmatched signal receiver

A memory device comprising:

• a receiver circuit to receive a data (DQ) signal and a data strobe (DQS) signal;
• circuitry including a ring oscillator and a copy of a data strobe (DQS) clock tree, the circuitry to:
• start the ring oscillator in response to a command from a memory controller,
• count a number of times the DQS signal propagates through the copy of the DQS clock tree, and
• stop the ring oscillator in response to a second command from the memory controller;
• and
• one or more registers to store a count from the ring oscillator.

A memory device comprising:

• a receiver circuit to receive a data (DQ) signal and to receive a clock signal;
• circuitry including a ring oscillator and a copy of a clock tree, the circuitry to:
• start the ring oscillator in response to a command from a memory controller,
• count a number of times the clock signal propagates through the copy of the clock tree, and
• stop the ring oscillator in response to a second command from the memory controller;
• and
• one or more registers to store a count from the ring oscillator.

A memory controller comprising:

• a transmitter circuit to:
• transmit a command to a memory device to start a data strobe (DQS) ring oscillator,
• transmit a second command to the memory device to stop the DQS ring oscillator, and
• transmit one or more commands to the memory device to read one or more mode registers, the one or more mode registers to store a result from a DQS ring oscillator counter;
• and
• circuitry to delay a data (DQ) signal relative to a data strobe (DQS) signal to the memory device based on the count from the DQS ring oscillator.

A memory controller comprising:

• a transmitter circuit to:
• transmit a command to a memory device to start a ring oscillator,
• transmit a second command to the memory device to stop the ring oscillator, and
• transmit one or more commands to the memory device to read one or more mode registers, the one or more mode registers to store a result of an oscillator counter;
• and
• circuitry to delay a data (DQ) signal relative to a clock signal to the memory device based on the count from the ring oscillator.