Method and circuit for self-training of a reference voltage and memory system including the same

A semiconductor device, comprising:

• at least a first memory chip including:
• at least a first buffer connected to receive an input signal and a reference voltage;
• at least a first reference voltage generator configured to output a reference voltage based on a first control code;
• and
• at least a first self-training circuit for determining an operational reference voltage to use during a normal mode of operation of the semiconductor device, wherein:
• an output from the first buffer is input to the first self-training circuit,
• the first control code is output from the first self-training circuit into the first reference voltage generator, and
• the first buffer, the first self-training circuit, and the first reference voltage generator form a loop.

A memory system comprising:

• a controller, the controller including a plurality of input/output pads configured to transmit a plurality of respective data signals;
• a memory device including a plurality of memory chips, each memory chip including a plurality of input/output pads respectively connected to the input/output pads of the controller;
• a plurality of buffers on each individual memory chip, each buffer connected to a respective input/output pad of the individual memory chip to receive an input signal, and each buffer outputting a buffer output signal;
• and
• a reference voltage generator on each individual memory chip, the reference voltage generator connected to at least one buffer on the respective individual memory chip,
• wherein the memory system is configured to perform reference voltage training on a first chip of the plurality of memory chips using output from a first i/o pad of the controller at the same time as performing reference voltage training on a second chip of the plurality of memory chips using output from a second i/o pad of the controller.