Techniques to mitigate bias drift for a memory device

An apparatus comprising:

• a controller for a memory device, the controller to include logic, at least a portion of which is implemented as hardware, the logic to:
• cause a first bias voltage to be applied to a first word-line coupled with a first memory cell included in the memory device and cause a second bias voltage to be applied to a bit-line coupled with the first memory cell, the first bias voltage and the second bias voltage to be applied during a write operation to program the first memory cell;
• and
• cause a third bias voltage to be applied to a second word-line coupled with a second memory cell included in the memory device during the write operation to program the first memory cell, the third bias voltage applied to the second word-line to cause a reduction in voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell, the third bias voltage less that the second bias voltage.