Apparatuses and methods for controlling data timing in a multi-memory system

An apparatus comprising:

• a first memory unit comprising a first memory control logic, a first memory and a first configurable delay circuit, the first memory control logic configured to receive a first read command and provide the first read command to the first memory, the first memory configured to receive the first read command and provide a first read data responsive to the first read command to a first output node;
• a second memory unit comprising a second memory control logic, a second memory and a second configurable delay circuit, the second memory control logic configured to receive a second read command subsequently issued from the first read command and provide the second read command to the second memory, the second memory configured to receive the second read command and provide a second read data responsive to the second read command to a second output node;
• and
• a through-silicon via (TSV) coupled to the first and second output nodes;
• wherein the first configurable delay circuit is configured to exhibit a first delay value and the second configurable delay circuit is configured to exhibit a second delay value such that the first read data and the second read data do not collide with each on the TSV.