Gate driving circuit

A gate driving circuit, applied to a liquid crystal display, comprising:

• an input terminal configured to receive a timing control signal including a total delay time;
• N delay units comprising a first delay unit, a second delay unit, . . . , a (N−1)-th delay unit and a N-th delay unit, wherein the first delay unit is coupled between the input terminal and the second delay unit;
• the second delay unit, . . . , a (N−1)-th delay unit and a N-th delay unit are connected in series to the first delay unit in order;
• delay times of the N delay units are adjustable and a sum of the delay times of the N delay units is the total delay time, the N delay units are divided into K delay unit groups, delay units in the same delay unit group have the same delay time;
• N and K are positive integers, N≧2 and N≧K;
• K control signal buses, coupled to the K delay unit groups respectively, configured to determine the delay times of the K delay unit groups respectively according to the timing control signal;
• N buffer units comprising a first buffer unit, a second buffer unit, . . . , an (N−1)-th buffer unit and an N-th buffer unit, wherein the first buffer unit is coupled between the input terminal and the first delay unit, the second buffer unit is coupled between the first delay unit and the second delay unit, . . . , the N-th buffer unit is coupled between the (N−1)-th delay unit and the N-th delay unit;
• and
• N output pads, correspondingly coupled to the N buffer units, configured to output N gate driving signals respectively.