Display apparatus
AssigneeSamsung Display Co., Ltd.
InventorsJAHUN KOO, HAKSUN KIM, KYUNG-HUN LEE
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Abstract
A display apparatus includes a display panel comprising a pixel which is connected to a gate line and a data line, a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal, and a gate controller configured to generate a clock signal having a duty ratio and to provide the gate driver with the clock signal, where a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.
Claims26
A display apparatus comprising:
- a display panel having a pixel connected between a gate line and a data line;
- a gate driver connected to the gate line and configured to generate a gate signal having at least one gate-on voltage and at least one gate-off voltage and to provide the gate line with the gate signal;
- and
- a gate controller connected to the gate driver and configured to generate a clock signal having at least one high level and at least one low level and to provide the gate driver with the clock signal,
- wherein a duty ratio of the clock signal in a vertical blanking period of a frame cycle is smaller than the duty ratio of the clock signal in an active period of the frame cycle.
A display apparatus comprising:
- a display panel comprising a pixel which is connected to a gate line and a data line;
- a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal;
- and
- a gate controller configured to generate a clock signal having a high level and low level and to provide the gate driver with the clock signal,
- wherein a high level of the clock signal in a vertical blanking period of a frame cycle is lower than a high level of the clock signal in an active period of the frame cycle.
A display apparatus comprising:
- a display panel comprising a pixel which is connected to a gate line and a data line;
- a gate driver configured to generate a gate signal having a gate-on voltage and a gate-off voltage and to provide the gate line with the gate signal;
- and
- a gate controller configured to generate a clock signal having a high level and a low level and to provide the gate driver with the clock signal,
- wherein the clock signal swings between the high level and the low level in an early portion and a late portion of the vertical blanking period, and maintains the low level in a middle portion of the vertical blanking period.
A display apparatus comprising:
- a display panel having a pixel connected between a gate line and a data line;
- a gate driver connected to the gate line and configured to generate a gate signal having at least one gate-on voltage and at least one gate-off voltage and to provide the gate line with the gate signal;
- and
- a gate controller connected to the gate driver and configured to generate a clock signal having at least one high level and at least one low level and to provide the gate driver with the clock signal,
- wherein a mean amplitude of the clock signal in a vertical blanking period of a frame cycle is smaller than the mean amplitude of the clock signal in an active period of the frame cycle.
Dependencies are inferred from the claim text.