A shift register unit, comprising two transfer gate modules, four AND gate modules, and two capacitor modules, as well as a pulse signal input terminal, four pulse signal output terminals, and a plurality of clock signal input terminals;
- a first terminal of a first capacitor module is connected to a first node;
- a first terminal of a second capacitor module is connected to a third node;
- a first input terminal of a first transfer gate module is connected to the pulse signal input terminal, a second input terminal of the first transfer gate module is connected to a first clock signal input terminal, a third input terminal of the first transfer gate module is connected to a second clock signal input terminal, and an output terminal of the first transfer gate module is connected to the first node;
- a first input terminal of a second transfer gate module is connected to a second node, a second input terminal of the second transfer gate module is connected to a third clock signal input terminal, a third input terminal of the second transfer gate module is connected to a fourth clock signal input terminal, and an output terminal of the second transfer gate module is connected to the third node;
- each transfer gate module is configured to be turned on when a first level is inputted to the second input terminal thereof and the third input terminal thereof is at a second level, so as to write a scan signal inputted to the first input terminal thereof to a node connected to the output terminal thereof;
- a level of the scan signal is the first level, the second level being opposite to the first level;
- a first input terminal of a first AND gate module is connected to a fifth clock signal input terminal, a second input terminal of the first AND gate module is connected to the second node, and an output terminal of the first AND gate module is connected to a first pulse signal output terminal;
- a first input terminal of a second AND gate module is connected to a sixth clock signal input terminal, a second input terminal of the second AND gate module is connected to the second node, and an output terminal of the second AND gate module is connected to a second pulse signal output terminal;
- a first input terminal of a third AND gate module is connected to a seventh clock signal input terminal, a second input terminal of the third AND gate module is connected to a fourth node, and an output terminal of the third AND gate module is connected to a third pulse signal output terminal;
- a first input terminal of the fourth AND gate module is connected to an eighth clock signal input terminal, a second input terminal of the fourth AND gate module is connected to the fourth node, and an output terminal of the fourth AND gate module is connected to a fourth pulse signal output terminal;
- each AND gate module is configured to output the first level through an output terminal thereof when both the first input terminal thereof and the second input terminal thereof are at the first level;
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- the second node is electrically connected to the first node, a level state of the second node is in synchronization with a level state of the first node;
- the fourth node is electrically connected to the third node, a level state of the fourth node is in synchronization with a level state of the third node.