Display panel, shift register circuit and driving method thereof

A driving method of a shift register circuit, wherein the shift register circuit comprises a first transistor configured to be turned on in response to a voltage signal at a first node to provide an input signal to a second node, a second transistor configured to be turned on in response to a first clock signal to provide the input signal to the first node, a third transistor configured to be turned on in response to the first clock signal to provide a charging signal to a second node, a fourth transistor configured to be turned on in response to a voltage signal at the second node to provide a first voltage signal to a third node, a fifth transistor configured to be turned on in response to a second clock signal to provide a voltage signal at the third node to the first node, a sixth transistor configured to be turned on in response to the voltage signal at the second node to provide the first voltage signal to a signal output terminal, a seventh transistor configured to be turned on in response to a voltage signal at a fourth node to provide the second clock signal to the signal output terminal, a first capacitor electrically connected between the fourth node and the signal output terminal, and a second capacitor electrically connected between the second node and the first voltage signal, and a voltage at the fourth node is positively correlated to a voltage at the first node, the driving method comprising:

• in a first stage, controlling, by the first clock signal, the input signal and the first voltage signal, the second transistor, the third transistor, and the seventh transistor to be turned off, controlling, by the second clock signal, the fifth transistor to be turned on, and transmitting, by the sixth transistor, the first voltage signal to the signal output terminal.

A display panel including a shift register circuit, wherein the shift register circuit comprises:

• a first transistor, configured to be turned on in response to a voltage signal at a first node, such that an input signal is provided to a second node;
• a second transistor, configured to be turned on in response to a first clock signal, such that the input signal is provided to the first node;
• a third transistor, configured to be turned on in response to the first clock signal, such that a charging signal is provided to a second node;
• a fourth transistor, configured to be turned on in response to a voltage signal at the second node, such that a first voltage signal is provided to a third node;
• a fifth transistor, configured to be turned on in response to a second clock signal, such that a voltage signal at the third node is provided to the first node;
• a sixth transistor, configured to be turned on in response to the voltage signal at the second node, such that the first voltage signal is provided to a signal output terminal;
• a seventh transistor, configured to be turned on in response to a voltage signal at a fourth node, such that the second clock signal is provided to the signal output terminal, wherein a voltage at the fourth node is positively correlated to a voltage at the first node;
• a first capacitor electrically connected between the fourth node and the signal output terminal;
• and
• a second capacitor electrically connected between the second node and the first voltage signal.