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US 2017/0287203 A1Published application
Reduced Precision Ray Traversal with Plane Reuse
AssigneeIntel Corporation
InventorsKarthik Vaidyanathan, Marco Salvi
Life of this patent
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Abstract
A computation for a parent node may be reused in a child node in a reduced precision bounding volume hierarchy ray traversal for graphics processing.
Claims30
A method comprising:
- reusing, in a child node, a computation for a parent node in a reduced precision bounding volume hierarchy ray traversal for graphics processing.
One or more non-transitory computer readable media storing instructions to perform a sequence comprising:
- reusing, in a child node, a computation for a parent node in a reduced precision bounding volume hierarchy ray traversal for graphics processing.
An apparatus comprising:
- a processor to reuse, in a child node, a computation for a parent node in a reduced precision bounding volume hierarchy ray traversal for graphics processing;
- and
- a memory coupled to said processor.
Dependencies are inferred from the claim text.