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US 2017/0287198 A1Published application
Directed acyclic graph path enumeration with application in multilevel instancing
AssigneeIntel Corporation
InventorLouis Feng
Life of this patent
Estimating the term…
Abstract
Embodiments provide for an apparatus including one or more processors having logic to enumerate a directed path through nodes of a directed acyclic graph, the logic to determine a key for a node and a path identifier for a directed path between nodes of the directed acyclic graph.
Claims23
An apparatus comprising:
- one or more processors including logic to enumerate a directed path through nodes of a directed acyclic graph, the logic to determine a key for a node and a path identifier for a directed edge between nodes of the directed acyclic graph.
A non-transitory machine-readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations to enumerate a directed path through a directed multi-level instancing graph, the operations including:
- popping a node of the directed multi-level instancing graph from a node queue;
- computing a key value for the node and assigning the key value to the node;
- recording a minimum path identifier to use in processing one or more children of the node;
- computing a next path identifier to use in processing one or more children of the node, the next path identifier greater than a current path identifier;
- for each child node of the node, updating the minimum path identifier and maximum path identifier for the child node;
- and
- pushing a child node onto the node queue after the minimum path identifier and maximum path identifier for the child node is updated for each parent of the child node.
4 more elements
A computing system comprising:
- one or more processors including logic to enumerate a directed path through nodes of a directed acyclic graph, the logic to determine a key for a node and a path identifier for a directed edge between nodes of the directed acyclic graph;
- and
- parallel renderer logic to render a shared geometric object using the directed acyclic graph, the directed acyclic graph a multi-level instancing graph to define multiple instances of the shared geometric object.
Dependencies are inferred from the claim text.