Compiler managed memory for image processor
AssigneeGoogle Inc.
InventorsAlbert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
Life of this patent
Estimating the term…
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AssigneeGoogle Inc.
InventorsAlbert Meixner, Hyunchul Park, Qiuling Zhu, Jason Rupert Redgrave
Estimating the term…
A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.
A processor comprising:
A computer program product, encoded on one or more non-transitory computer storage media, comprising instructions that when executed by a processor comprising:
A method performed by a processor comprising:
Dependencies are inferred from the claim text.