Method and apparatus for performing protected walk based shadow paging

A method comprising:

• mapping a multiple level first stage page tables structure in second stage page tables, the multiple level page tables structure including a level one (L1) page table and a level two (L2) page table;
• storing a protected table walk (PTW) bit in a hypervisor configuration register (HCR);
• when the page tables of the multiple level page tables structure are marked according to a first attribute:
• permitting an operating system (OS) to write to at least one entry in the page tables of the multiple level page tables structure,
• blocking a memory management unit (MMU) from reading from the page tables of the multiple level page tables structure for translation,
• when the MMU attempts to read the page tables of the multiple level page tables structure for translation, trapping an event to an isolated security monitor, and
• in response to trapping the event to the isolated security monitor, verifying the page tables of the multiple level page tables structure for translation and changing the marking of the page tables of the multiple level page tables structure according to a second attribute, enabling the MMU to subsequently read from the page tables of the multiple level page tables structure for translation;
• and
• when the page tables of the multiple level page tables structure are marked according to the second attribute:
• permitting the OS to read from the page tables of the multiple level page tables structure for translating from a virtual address to an intermediate physical address (IPA) to a physical address,
• blocking the OS from writing to the page tables of the multiple level page tables structure, and
• in response to blocking the OS, updating the entries of the page tables of the multiple level page tables structure and changing the marking of subsequent page tables of the multiple level page tables structure according to the first attribute, enabling the OS to subsequently write to the page tables of the multiple level page tables structure,
• wherein the marking of the subsequent page tables includes at least one of:
• marking the L2 page table for entries in the L1 page table or marking an L3 page table for entries in the L2 page table.

A system comprising:

• a processor;
• a computer readable medium electronically coupled to the processor;
• and a plurality of instructions wherein at least a portion of the plurality of instructions are storable in the computer readable medium, and wherein the plurality of instructions are configured to cause the processor to perform the steps of:
• controlling an operating system to translate from a virtual address to an Intermediate Physical Address (IPA) using first stage page tables, wherein the first stage page tables comprises a multiple level page tables structure that includes a level one (L1) page table and a level two (L2) page table;
• and
• controlling a hypervisor to translate from the IPA to a Physical Address, the hypervisor comprising:
• second stage page tables configured to store the L1 and L2 page tables according to different memory attributes;
• a hypervisor configuration register (HCR) configured to store a protected table walk (PTW) bit;
• and
• when the L1 page table is marked according to a first attribute:
• (i) permitting the OS to write to at least one entry in the L1 page table, (ii) blocking a memory management unit (MMU) from reading from the L1 page table for translation, and (iii) when the MMU attempts to read the L1 page table for translation, trapping an event to an isolated security monitor, and (iv) in response to trapping the event to the isolated security monitor, verifying the L1 page table for translation and changing the marking of the L1 page table according to a second attribute, enabling the MMU to subsequently read from the L1 page table for translation;
• and
• when the L1 page table is marked according to the second attribute:
• (i) permitting the OS to read from the L1 page table for translating from a virtual address to an intermediate physical address (IPA) to a physical address, (ii) blocking the OS from writing to the L1 page table, (iii) when the OS attempts to write to the L1 page table for translation, trapping an event to an isolated security monitor, and (iv) in response to trapping the event to the isolated security monitor, blocking the OS, updating the L1 page table and changing the marking of the L2 page table that is pointed to by the updated L1 page table entry according to the first attribute, enabling the OS to subsequently write to the L2 page table and repeat for L2 page tables and any subsequent levels of page tables.