Systems and methods for creating block constraints in integrated circuit designs

A timing analysis module for generating constraints associated with an integrated circuit design based on floor-planning data associated with the integrated circuit design, the timing analysis module comprising:

• a processor;
• a memory configured to store software instructions that, when executed by the processor, cause the processor to:
• parse the floor-planning data to determine a plurality of blocks in the integrated circuit design, cell data specifying one or more cells included in each of the plurality of blocks, and interconnect data specifying one or more electrical interconnects between the plurality of blocks;
• identify a plurality of paths, each of the paths specifying a first block, a second block, and a first interconnect between the first block and the second block;
• determine cycle time criteria for each of the plurality of paths;
• estimate a total delay for each of the plurality of paths based on a block-to-block delay and an in-block delay, wherein the block-to-block delay is based on the interconnect data associated with the first interconnect, and the in-block delay is based on the cell data associated with the first and second blocks;
• and
• generate a set of constraints for the integrated circuit design only if the total delay for each of the identified paths meets the corresponding cycle time criteria for that path.