Pattern matching circuit

A pattern matching circuit comprising:

• a memory array to store a plurality of bits, wherein the memory array is to implement a pattern matching filter for a plurality of reference strings;
• and
• pattern matching filter logic coupled to the memory array, the pattern matching circuitry to:
• receive a string;
• generate first and second addresses using first and second hash functions, wherein the first and second addresses are configured to correspond to bits of the memory array in a same column;
• and
• read the bits of the memory array associated with the first and second addresses to determine whether the string is a potential match with one of the reference strings.

A system comprising:

• a processor;
• and
• a pattern matching filter coupled to the processor, the pattern matching filter including:
• a memory array having a plurality of memory cells, wherein the memory array is to implement a pattern matching filter for a plurality of reference strings;
• a read circuit coupled to the memory array and the processor, wherein the read circuit includes a plurality of read pulldowns coupled to respective memory cells of the memory array and coupled to a same local bitline associated with a column of the memory array, the individual read pulldowns to be activated by respective wordlines;
• and
• first and second row decoders to generate wordline signals to simultaneously activate two of the read pulldowns to generate an output signal that indicates whether an input string is a potential match for one or more of the reference strings.