Semiconductor memory device, storage system, and computer

A storage system comprising:

• a plurality of semiconductor memory devices;
• and
• a device controller configured to transmit an I/O request to each of the plurality of semiconductor memory devices,
• the plurality of semiconductor memory devices each including,
• a semiconductor memory including a plurality of semiconductor memory portions,
• a memory controller configured to control the semiconductor memory,
• a first switching circuit which is coupled to the plurality of semiconductor memory portions and to the memory controller and with which a data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and
• a second switching circuit which is coupled to the plurality of semiconductor memory portions and to the memory controller and with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and
• in each of the one or more semiconductor memory devices, the first and second switching circuits being configured to share a switching signal for switching a coupling destination of a switching circuit,
• in each of the one or more semiconductor memory devices, the non-data system signal line for each of the plurality of semiconductor memory portions is a signal line, in which a signal that indicates an operation state of the semiconductor memory portion and that is received by the memory controller is transmitted,
• in each of the one or more semiconductor memory devices, in a case where the coupling destination of the first and second switching circuits is a first semiconductor memory portion that is one of the plurality of semiconductor memory portions, the first semiconductor memory portion is a transmission destination, and a command wait state has been detected with respect to the first semiconductor memory portion, the memory controller is configured to:
• wait for detection of transition of the first semiconductor memory portion to a processing in-progress state based on a received operation state signal, after transmission of a data system signal to the first semiconductor memory portion;
• and
• switch the coupling destination of the first and second switching circuits to any of the semiconductor memory portions other than the first semiconductor memory portion by using the switching signal, after detecting the transition of the first semiconductor memory portion to the processing in-progress state.

A computer comprising:

• a semiconductor memory device;
• and
• a processor configured to transmit an I/O request to the semiconductor memory device,
• the semiconductor memory device including,
• a semiconductor memory including a plurality of semiconductor memory portions,
• a memory controller configured to control the semiconductor memory,
• a first switching circuit which is coupled to the plurality of semiconductor memory portions and to the memory controller, and with which a data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and
• a second switching circuit which is coupled to the plurality of semiconductor memory portions and the memory controller, and with which a non-data system signal line between the plurality of semiconductor memory portions and the memory controller is branched, and
• in the semiconductor device, the first and second switching circuits being configured to share a switching signal for switching a coupling destination of a switching circuit,
• in the semiconductor memory device, the non-data system signal line for each of the plurality of semiconductor memory portions is a signal line, in which a signal that indicates an operation state of the semiconductor memory portion and that is received by the memory controller is transmitted,
• in the semiconductor memory device, in a case where the coupling destination of the first and second switching circuits is a first semiconductor memory portion that is one of the plurality of semiconductor memory portions, the first semiconductor memory portion is a transmission destination, and a command wait state has been detected with respect to the semiconductor memory portion, the memory controller is configured to:
• wait for detection of transition of the first semiconductor memory portion to a processing in-progress state based on a received operation state signal, after transmission of a data system signal to the first semiconductor memory portion;
• and
• switch the coupling destination of the first and second switching circuits to any of the semiconductor memory portions other than the first semiconductor memory portion by using the switching signal, after detecting the transition of the first semiconductor memory portion to the processing in-progress state.