Dynamically Reconfigurable Analog Routing and Multiplexing Architecture on a System on a Chip

A method comprising:

• receiving first analog routing data from at least one processor circuit;
• receiving second analog routing data from a programmable logic section comprising a plurality of digital programmable blocks formed in an integrated circuit;
• configuring a dynamically or statically reconfigurable analog routing fabric on the integrated circuit according to the first analog routing data and the second analog routing data to selectively enable connections and disconnections between one or more of a plurality of analog circuit blocks and a plurality of input/output (I/O) pins through a plurality of I/O connection circuits corresponding to the plurality of I/O pins;
• and
• configuring the dynamically or statically reconfigurable analog routing fabric to selectively connect a first analog circuit block of the plurality of analog circuit blocks with a second analog circuit block of the plurality of analog circuit blocks to provide an analog function.

A system comprising:

• a plurality of external connection pins;
• a digital section coupled to a first subset of the plurality of external connection pins, the digital section comprising a processor circuit, a memory circuit and a plurality of digital programmable blocks;
• and
• an analog section coupled to a second subset of the plurality of external connection pins, the analog section comprising a plurality of analog circuit blocks and a dynamically or statically reconfigurable analog routing fabric configured to selectively connect and disconnect one or more of the plurality of analog circuit blocks the second subset of the plurality of external connection pins through a plurality of input/output (I/O) connection circuits in response to first analog routing data received from the processor circuit and second analog routing data received from the plurality of digital programmable blocks, and to selectively connect a first analog circuit block of the plurality of analog circuit blocks with a second analog circuit block of the plurality of analog circuit blocks to provide an analog function.

A integrated circuit comprising:

• a plurality of input/outputs (I/Os);
• a digital section selectively coupled to a first subset of the plurality of I/Os, the digital section comprising a processor circuit, a memory circuit and a plurality of digital programmable blocks;
• and
• an analog section selectively coupled to a second subset of the plurality of I/Os, the analog section comprising a plurality of analog circuit blocks and a dynamically or statically reconfigurable analog routing fabric configured to selectively connect and disconnect one or more of the plurality of analog circuit blocks to the second subset of the plurality of I/Os in response to first analog routing data received from the processor circuit and second analog routing data received from the plurality of digital programmable blocks, and to selectively connect a first analog circuit block of the plurality of analog circuit blocks with a second analog circuit block of the plurality of analog circuit blocks to provide an analog function.