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US 2017/0286334 A1Published application
Enhanced directed system management interrupt mechanism
AssigneeIntel Corporation
InventorsGaurav Khanna, Prashant Sethi, Venkatesh Ramamurthy
Life of this patent
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Abstract
A method is described. The method includes determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state, triggering a SMI for the first processor core, the first processor core entering a system management mode (SMM) and performing one or more platform management operations.
Claims25
A compute node comprising:
- a plurality of processor cores, each including;
- an operating system (OS) having an OS power management (OSPM) engine to determine that a first of the plurality of processor cores has entered an idle state;
- and
- a system management mode (SMM) handler to detect a system management interrupt (SMI) and transition control of hardware resources of the first processor core from the OS to a basic input output system (BIOS) to enter a system management mode (SMM) in order to perform one or more platform management operations.
1 more element
A directed system management interrupt (SMI) method comprising:
- determining that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state;
- triggering a SMI for the first processor core;
- the first processor core entering a system management mode (SMM);
- and
- performing one or more platform management operations.
2 more elements
At least one computer readable medium having instructions, which when executed by one or more processors, cause the processors to:
- determine that a first of a plurality of processor cores in a multi-processor computing system has entered an idle state;
- trigger a SMI for the first processor core;
- enter the first processor core into a system management mode (SMM);
- and
- perform one or more platform management operations.
2 more elements
Dependencies are inferred from the claim text.