US 2017/0286333 A1 · Arbiter Based Serialization of Processor System Management Interrupt Events

Abstract

A processor includes cores to execute instructions, and circuitry to detect a system management interrupt (SMI) event on the processor, direct an indication of the SMI event to an arbiter on a controller hub, and receive an interrupt signal from the arbiter. The processor also includes an SMI handler to take action in response to the interrupt, and circuitry to communicate the interrupt signal to the cores. The cores include circuitry to pause while the SMI handler responds to the interrupt. The interrupt handler includes circuitry to determine that a second SMI event detected on the processor or controller hub is pending, and to take action in response. The interrupt handler includes circuitry to set an end-of-SMI bit to indicate that the interrupt handler has completed its actions. The controller includes circuitry to prevent the arbiter from issuing another interrupt to the processor while this bit is false.

Claims20

Dependent claims

A processor, comprising:

a core including circuitry to execute instructions;
and
circuitry to:
detect, on the processor, a first system management interrupt (SMI) event of a first SMI event type;
direct an indication of the first SMI event to an arbiter that is outside the processor;
receive an interrupt signal from the arbiter;
an interrupt handler to respond to the interrupt signal, including circuitry to:
take action in response to detection of the first SMI event, the action to be dependent on the first SMI event type;
and
effect an indication that the interrupt handler has completed its actions in response to the interrupt signal.

7 more elements

Dependencies are inferred from the claim text.

Arbiter Based Serialization of Processor System Management Interrupt Events

Life of this patent

Arbiter Based Serialization of Processor System Management Interrupt Events

Life of this patent

Abstract

Claims20