US 2017/0286332 A1 · TECHNOLOGIES FOR PROCESSOR CORE SOFT-OFFLINING

Abstract

Technologies for processor core soft-offlining include a computing device having a processor with multiple processor cores. On boot, an operating system queries a firmware interface to retrieve a potential offline set of processor cores. The operating system prevents the processor cores of the potential offline set from receiving device interrupts. The computing device detects a platform management event from the firmware interface and, in response to the platform management event, queries the firmware interface to determine a requested offline set of processor cores. Each of the processor cores in the requested offline set is included in the potential offline set. The computing device brings the processor cores of the requested offline set into a low-power state, and then the computing device may start performing a platform management operation. The platform management event may include a memory hot-plug event or a specialized workload event. Other embodiments are described and claimed.

Claims25

Dependent claims

A computing device for processor core offlining, the computing device comprising:

a configuration module to query a firmware interface of the computing device to retrieve a first set of processor cores of the computing device, wherein each of the first set of processor cores is a potential target to soft-offline;
an interrupt management module to prevent receipt of device interrupts by the processor cores of the first set of processor cores;
and
a core management module to (i) detect, in response to prevention of receipt of device interrupts by the processor cores of the first set of processor cores, a platform management event from the firmware interface and (ii) query the firmware interface to determine a second set of processor cores to bring offline in response to detection of the platform management event, wherein the second set of processor cores is included in the first set of processor cores.

1 more element

A method for processor core offlining, the method comprising:

querying, by a computing device, a firmware interface of the computing device to retrieve a first set of processor cores of the computing device, wherein each of the first set of processor cores is a potential target for soft-offlining;
preventing, by the computing device, the processor cores of the first set of processor cores from receiving device interrupts;
detecting, by the computing device in response to preventing the processor cores of the first set of the processor cores from receiving device interrupts, a platform management event from the firmware interface;
and
querying, by the computing device, the firmware interface to determine a second set of processor cores to bring offline in response to detecting the platform management event, wherein the second set of processor cores is included in the first set of processor cores.

2 more elements

One or more computer-readable storage media comprising a plurality of instructions that in response to being executed cause a computing device to:

query a firmware interface of the computing device to retrieve a first set of processor cores of the computing device, wherein each of the first set of processor cores is a potential target for soft-offlining;
prevent the processor cores of the first set of processor cores from receiving device interrupts;
detect, in response to preventing the processor cores of the first set of the processor cores from receiving device interrupts, a platform management event from the firmware interface;
and
query the firmware interface to determine a second set of processor cores to bring offline in response to detecting the platform management event, wherein the second set of processor cores is included in the first set of processor cores.

2 more elements

Dependencies are inferred from the claim text.

Technologies for processor core soft-offlining

Life of this patent

Technologies for processor core soft-offlining

Life of this patent

Abstract

Claims25