Read training a memory controller
AssigneeIntel Corporation
InventorsTonia G. MORRIS, Jonathan C. JASPER, Arnaud J. FORESTIER
Life of this patent
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Abstract
Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.
Claims18
1-20. (canceled)
An integrated circuit device comprising:
- a first interface to communicate with a memory controller over a bus interface and a second interface to communicate with one or more memory chips;
- and
- memory module controller logic to perform operations comprising, to:
- receive a request from the memory controller to initiate a training mode;
- transmit continuous bit patterns on a side band lane of the bus interface to the memory controller in response to receiving the request from the memory controller;
- receive a request from the memory controller to end the training mode;
- and
- discontinue the transmission of the continuous bit patterns on the side band lane in response to receiving a request from the memory controller.
A system comprising:
- a processor;
- a memory controller, wherein the processor communicates memory access requests to the memory controller;
- a memory module including:
- one or more memory chips;
- and
- a first interface to communicate with the memory controller over a bus interface and a second interface to communicate with the one or more memory chips;
- and
- memory module controller logic to perform operations comprising, to:
- receive a request from the memory controller to initiate a training mode;
- transmit continuous bit patterns on a side band lane of the bus interface to the memory controller in response to receiving the request from the memory controller;
- receive a request from the memory controller to end the training mode;
- and
- discontinue the transmission of the continuous bit patterns on the side band lane in response to receiving a request from the memory controller.
A method for read training a memory module, comprising:
- receiving a request from the memory controller to initiate a training mode;
- transmitting continuous bit patterns on a side band lane of a bus interface to the memory controller in response to receiving the request from a memory controller;
- receiving a request from the memory controller to end the training mode;
- and
- discontinuing the transmission of the continuous bit patterns on the side band lane in response to receiving a request from the memory controller.
Dependencies are inferred from the claim text.