Multi-Standard Single Interface With Reduced I/O Count

An apparatus, comprising:

• a plurality of processors;
• a memory controller coupled to said plurality of processors;
• a system memory coupled to said memory controller;
• I/O control logic circuitry coupled to said memory controller, said I/O control logic circuitry including an electrical interface that supports a first specification and a second specification, said first specification specifying differentially transmitted data, said second specification specifying at least three transmitted data signals, said electrical interface comprising a plurality of modular transmitter circuits, each transmitter circuit comprising a single ended driver and a select circuit, said select circuit to select either one end of a differential signal associated with said first specification or one of said at least three transmitted data signals associated with said second specification.