Memory protection at a thread level for a memory protection key architecture
AssigneeIntel Corporation
InventorsFrancesc Bernat Guim, David A. Koufaty, Andrea Pellegrini, Rajesh M. Sankaran
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AssigneeIntel Corporation
InventorsFrancesc Bernat Guim, David A. Koufaty, Andrea Pellegrini, Rajesh M. Sankaran
Estimating the term…
A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management unit includes a storage unit to store a page table entry including an identifier of a memory domain and a protection key associated with the identifier. The protection key indicates whether a memory page in the memory domain is accessible. The IO memory management unit also includes a protection key register comprising a field indexed by the protection key, the field including a set of bits reflecting a memory access permission associated with the protection key. The protection key register is, responsive to receiving a request from an IO device to store data associated with the process or the thread of the process, to one of allow or deny permission to access the memory page in the memory domain for storage of the data associated with the process or the thread of the process based on the protection key.
A processing device comprising:
A system-on-a chip (SoC) comprising:
A system comprising:
A method comprising:
Dependencies are inferred from the claim text.