Memory access protection apparatus and methods
AssigneeApple Inc.
InventorsSaurabh Garg, Karan Sanghi, Vladislav Petkov, Haining Zhang
Life of this patent
Estimating the term…
Abstract
Methods and apparatus for providing access to a shared memory resource. In one embodiment, a first processor generates a first window register associated with the shared memory resource; and transmits the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor without requiring a performance of arbitration operations by the first processor.
Claims20
A method for providing access to a shared memory resource, comprising:
- generating, by a first processor, a first window register associated with the shared memory resource;
- and
- transmitting the first window register from the first processor to a second processor, the first window register defining a first extent of address space within the shared memory resource that is directly accessible by the second processor.
A computing device comprising a memory mapped system, the computing device comprising:
- a host processing device comprising a host CPU and a host memory management unit (MMU);
- a peripheral processing device comprising a peripheral CPU, a peripheral MMU, peripheral memory and a peripheral direct memory access (DMA) unit;
- and
- a host memory accessible by both the host processing device and the peripheral processing device;
- wherein the host processing device further comprises logic configured to:
- generate a first window register associated with the host memory;
- and
- transmit the first window register from the host processing device to the peripheral processing device, the first window register defining a first extent of address space within the host memory that is directly accessible by the peripheral processing device.
A peripheral processing device configured to access host memory within a memory mapped system, the peripheral processing device comprising:
- a peripheral CPU, a peripheral MMU, peripheral memory and a peripheral direct memory access (DMA) unit and further comprising logic configured to:
- receive a first window register from a host processing device, the first window register defining a first extent of address space within the host memory resource that is directly accessible by the peripheral processing device.
Dependencies are inferred from the claim text.