Avoiding redundant memory encryption in a cryptographic protection system

A method for cryptographic memory protection, comprising:

• receiving an access request at processing circuitry in a device to access a memory location in memory circuitry in the device, the memory circuitry including a first region in which encrypted data associated with at least one trusted execution environment is stored, a second region in which encrypted data associated with general memory is stored and at least one memory location in which encrypted data received via direct memory access is stored;
• determining, in encryption circuitry within the processing circuitry, the setting of at least one indicator bit corresponding to the data or the memory location;
• and
• avoiding redundant memory encryption by controlling, in the encryption circuitry, at least one of a first encryption engine in the encryption circuitry to perform data encryption and decryption for the first region or a second encryption engine to perform data encryption and decryption for the second region of the memory circuitry.

At least one machine-readable storage medium having stored thereon, individually or in combination, instructions for cryptographic memory protection that, when executed by one or more processors, cause the one or more processors to:

• receive an access request at processing circuitry in a device to access a memory location in memory circuitry in the device, the memory circuitry including a first region in which encrypted data associated with at least one trusted execution environment is stored, a second region in which encrypted data associated with general memory is stored and at least one memory location in which encrypted data received via direct memory access is stored;
• determine, in encryption circuitry within the processing circuitry, the setting of at least one indicator bit corresponding to the data or the memory location;
• and
• avoid redundant memory encryption by controlling, in the encryption circuitry, at least one of a first encryption engine in the encryption circuitry to perform data encryption and decryption for the first region or a second encryption engine to perform data encryption and decryption for the second region of the memory circuitry.