Apparatus and method for lazy translation lookaside buffer (tlb) coherence
AssigneeIntel Corporation
InventorsKSHITIJ A. DOSHI, CHRISTOPHER J. HUGHES
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Abstract
An apparatus and method are described for managing TLB coherence. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; one or more epoch counters each programmed with a specified epoch value; and TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value.
Claims24
A processor comprising:
- one or more cores to execute instructions and process data;
- one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions;
- one or more epoch counters each programmed with a specified epoch value;
- and
- TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value.
A method comprising:
- executing instructions on a set of one or more cores to execute instructions and process data;
- caching virtual-to-physical address translations usable by the set of one or more cores within one or more translation lookaside buffers (TLBs) when executing the instructions;
- programming one or more epoch counters with specified epoch values;
- and
- validating a specified set of TLB entries at intervals specified by one or more of the epoch values.
A system comprising:
- a memory to store instructions and data;
- a processor to execute the instructions and process the data;
- a graphics processor to perform graphics operations in response to graphics instructions;
- a network interface to receive and transmit data over a network;
- an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input;
- the processor comprising:
- one or more cores to execute instructions and process data;
- one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions;
- one or more epoch counters each programmed with a specified epoch value;
- and
- TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value.
Dependencies are inferred from the claim text.