Pipelined Prefetcher for Parallel Advancement Of Multiple Data Streams

A method, comprising, in a processor:

• receiving an instruction;
• decoding the instruction;
• executing the instruction, including:
• receiving a first demand request for data at a first memory address, the data at the first memory address being for consumption while executing the first instruction, and the first memory address being within a first line in a memory;
• providing, in response to receiving the first demand request, the data at the first memory address for consumption during the executing;
• prefetching into a first cache in a cache hierarchy, in response to receiving the first demand request, a second line in the memory at a first offset distance from the first line;
• prefetching into a second cache in the cache hierarchy, in response to receiving the first demand request, a third line in the memory at a second offset distance from the second line, the third line being farther from the first line than is the second line;
• and
• retiring the instruction.

A system, comprising:

• a memory;
• and
• a processor, including:
• a front end including circuitry to decode an instruction;
• an execution unit including circuitry to execute the instruction;
• a mid-level cache in a cache hierarchy;
• a last-level cache in the cache hierarchy, the last-level cache to be at a lower level in the cache hierarchy than the mid-level cache;
• a prefetcher, including circuitry to:
• receive a first demand request for data at a first memory address, the data at the first memory address to be consumed by execution of the instruction, and the first memory address to be within a first line in a memory;
• provide, in response to the first demand request, the data at the first memory address to the execution unit for consumption by the execution of the instruction;
• prefetch into the mid-level cache, in response to the first demand request, a second line in the memory at a first offset distance from the first line;
• prefetch into the last-level cache, in response to the first demand request, a third line in the memory at a second offset distance from the second line, the third line to be farther from the first line than is the second line;
• and
• a retirement unit to retire the instruction.