US 2017/0286303 A1 · PREFETCH MECHANISM FOR SERVICING DEMAND MISS

Abstract

Systems and methods relate to servicing a demand miss for a cache line in a first cache (e.g., an L1 cache) of a processing system, for example, when none of one or more fill buffers for servicing the demand miss are available. In exemplary aspects, the demand miss is converted to a prefetch operation to prefetch the cache line into a second cache (e.g., an L2 cache), wherein the second cache is a backing storage location for the first cache. Thus, servicing the demand miss is not delayed until a fill buffer becomes available, and once a fill buffer becomes available, the prefetched cache line is returned from the second cache to the available fill buffer.

Claims30

Dependent claims

A method of cache access in a processing system, the method comprising:

determining that there is a first demand miss for a first cache line in a first cache;
and
when no fill buffer is available to service the first demand miss, converting the first demand miss into a prefetch operation for prefetching the first cache line into a second cache.

Dependencies are inferred from the claim text.

Facts

Application

15/087,649Filed 31 Mar 2016

Published

5 Oct 2017

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 12/0862
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with prefetch
G06F 12/0811
Multiuser, multiprocessor or multiprocessing cache systems: with multilevel cache hierarchies
G06F 12/0891
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 12/0897
Caches characterised by their organisation or structure: with two or more cache hierarchy levels

Prefetch mechanism for servicing demand miss

Life of this patent

Prefetch mechanism for servicing demand miss

Life of this patent

Abstract

Claims30