Method, system, and apparatus for a coherency task list to minimize cache snooping between cpu and fpga
AssigneeIntel Corporation
InventorsStephen S. Chang, Pratik M. Marolia
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AssigneeIntel Corporation
InventorsStephen S. Chang, Pratik M. Marolia
Estimating the term…
Method and system implementing a task list in a cache agent for reducing cache line snoops. One embodiment comprises: monitoring a list of tasks that is stored in a shared cache memory and shared by a plurality of cache agents, wherein each task in the list of tasks is associated with at least a data block, a task command, and a task state, and wherein the list of tasks is fully coherent amongst the plurality of cache agents and the data block associated with each task is not coherent amongst the plurality of cache agents; detecting an access to the list of tasks and responsive to the detecting, snoop the list of tasks to generate a response, wherein the response comprises performing the task command of the accessed task on the associated data block to generate a result and storing the result in the same or different data block.
A method implemented in a shared cache memory system, the method comprising:
A shared cache memory system comprising:
Dependencies are inferred from the claim text.