Apparatus and method for triggered prefetching to improve i/o and producer-consumer workload efficiency

A processor comprising:

• an I/O interface circuit to access a first set of cache lines in a first cache;
• a core comprising a second cache to store a second set of cache lines;
• a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the I/O interface circuit;
• a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.

A system comprising:

• a memory to store instructions and data;
• a processor to execute the instructions and process the data;
• a graphics processor to perform graphics operations in response to graphics instructions;
• a network interface to receive and transmit data over a network;
• an interface for receiving user input from a mouse or cursor control device, the plurality of cores executing the instructions and processing the data responsive to the user input;
• the processor comprising:
• a first core comprising a first cache to store a first set of cache lines;
• a second core comprising a second cache to store a second set of cache lines;
• a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache;
• a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.