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US 2017/0286218 A1Published application
Semiconductor devices, and semiconductor systems
AssigneeSK hynix Inc.
InventorChang Hyun KIM
Life of this patent
Estimating the term…
Abstract
A write parity signal generation circuit, semiconductor device and semiconductor system may be provided. The write parity signal generation circuit may be configured to generate a pre-parity signal from a write data signal and a read data signal, and generate a write parity signal from the pre-parity signal and a syndrome signal.
Claims21
A semiconductor device comprising:
- a write parity signal generation circuit configured to generate a pre-parity signal from a write data signal and a read data signal and configured to generate a write parity signal from the pre-parity signal and a syndrome signal based on a control signal, if a mask write operation is performed;
- and
- a data error correction circuit configured to generate the syndrome signal from the read data signal and a read parity signal and configured to generate the control signal according to an error position of the read data signal included in the syndrome signal and a masked position of the write data signal included in an internal data mask signal.
A semiconductor device comprising:
- a memory core circuit configured to generate a read data signal and a read parity signal from a storage region corresponding to an internal address signal based on a write command signal and an internal data mask signal, if a mask write operation is performed;
- and
- a write parity signal generation circuit configured to generate a pre-parity signal from a write data signal and the read data signal and configured to generate a write parity signal from the pre-parity signal and a syndrome signal based on a control signal, if the mask write operation is performed.
Dependencies are inferred from the claim text.