US 2017/0286214 A1 · PROVIDING SPACE-EFFICIENT STORAGE FOR DYNAMIC RANDOM ACCESS MEMORY (DRAM) CACHE TAGS

Abstract

Providing space-efficient storage for dynamic random access memory (DRAM) cache tags is provided. In one aspect, a DRAM cache management circuit provides a plurality of cache entries, each of which contains a tag storage region, a data storage region, and an error protection region. The DRAM cache management circuit is configured to store data to be cached in the data storage region of each cache entry. The DRAM cache management circuit is also configured to use an error detection code (EDC) instead of an error correcting code (ECC), and to store a tag and the EDC for each cache entry in the error protection region of the cache entry. In this manner, the capacity of a DRAM cache can be increased by avoiding the need for the tag storage region for each cache entry, while still providing error detection for the cache entry.

Claims20

Dependent claims

A processor-based system, comprising:

a dynamic random access memory (DRAM) cache that is part of a high-bandwidth memory, the DRAM cache comprising a plurality of cache entries each providing a data storage region and an error protection region;
and
a DRAM cache management circuit located on a compute die of the processor-based system and communicatively coupled to the DRAM cache;
the DRAM cache management circuit configured to:
write data to be cached in the data storage region of a cache entry of the plurality of cache entries of the DRAM cache;
and
write a tag and an error detection code (EDC) for the cache entry in the error protection region of the cache entry.

4 more elements

A method for providing space-efficient storage of dynamic random access memory (DRAM) cache tags in a DRAM cache, comprising:

writing, by a DRAM cache management circuit, data to be cached in a data storage region of a cache entry of a plurality of cache entries of a DRAM cache that is part of a high-bandwidth memory;
and
writing a tag and an error detection code (EDC) for the cache entry in an error protection region of the cache entry.

A non-transitory computer-readable medium having stored thereon computer executable instructions which, when executed by a processor, cause the processor to:

write data to be cached in a data storage region of a cache entry of a plurality of cache entries of a dynamic random access memory (DRAM) cache that is part of a high-bandwidth memory;
and
write a tag and an error detection code (EDC) for the cache entry in an error protection region of the cache entry.

Dependencies are inferred from the claim text.

Providing space-efficient storage for dynamic random access memory (dram) cache tags

Life of this patent

Providing space-efficient storage for dynamic random access memory (dram) cache tags

Life of this patent

Abstract

Claims20