Handling of Error Prone Cache Line Slots Of Memory Side Cache of Multi-Level System Memory

A computing system, comprising:

• a plurality of processing cores;
• a display;
• a multi-level system memory;
• memory controller logic circuitry to interface with a memory side cache of said multi-level system memory, said memory controller logic circuitry comprising error tracking circuitry to track errors of cache line slots in said memory side cache, said memory controller logic circuitry also comprising faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone, said memory controller logic circuitry to declare a miss in said memory side cache for requests that map to cache line slots identified in said faulty list.

A method, comprising:

• tracking errors of cache line slots of a memory side cache of a multi-level system memory;
• identifying a cache line slot that demonstrates excessive errors;
• identifying said cache line slot on a faulty list;
• receiving a request for a cache line that maps to said cache line slot;
• recognizing that said cache line slot is identified on said faulty list and declaring a miss in said memory side cache for said request in response.