Validation of memory on-die error correction code

One or more non-transitory computer-readable storage mediums having stored thereon data representing sequences of instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

• writing a first test value in a computer memory;
• generating a first set of ECC (error correction code) code bits by an on-die ECC logic of the computer memory in response to the writing of the first test value;
• blocking generation of ECC code bits by a memory controller of the computer memory;
• and
• writing a second test value in the computer memory, the second test value differing from the first test value by one or more bits.

A computing system comprising:

• one or more processors;
• and
• synchronous dynamic random access memory (SDRAM) for the storage of data, the SDRAM including a memory device having:
• one or more memory arrays for the storage of data,
• control logic to control operation of the memory device, and
• ECC (error correction code) logic, including ECC correction logic to correct data and ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays;
• wherein, in a validation mode to validate operation of the ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value.