Operation of a multi-slice processor implementing a hardware level transfer of an execution thread

A multi-slice processor comprising:

• a plurality of execution slices, wherein the multi-slice processor is configured to carry out the steps of:
• responsive to a thread switch signal:
• halting dispatch of one or more instructions retrieved from an instruction cache;
• generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice;
• and
• dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache;
• and
• transferring, in dependence upon executing the plurality of instructions, the execution thread from the first execution slice to the second execution slice.

An apparatus comprising:

• a multi-slice processor that includes a plurality of execution slices;
• and
• a computer memory operatively coupled to the multi-slice processor, wherein the multi-slice processor is configured to carry out the steps of:
• responsive to a thread switch signal:
• halting dispatch of one or more instructions retrieved from an instruction cache;
• generating a plurality of instructions to transfer an execution thread from a first execution slice to a second execution slice;
• and
• dispatching the plurality of instructions instead of the one or more instructions retrieved from the instruction cache;
• and
• transferring, in dependence upon executing the plurality of instructions, the execution thread from the first execution slice to the second execution slice.