US 2017/0286157 A1 · Work Conserving, Load Balancing, and Scheduling

Abstract

A system and method are described for work conserving, load balancing, and scheduling by a network processor. For example, one embodiment of a system includes a plurality of processing cores, including a scheduling circuit, at least one source processing core that generates at least one task and at least one destination processing core that receives and processes the at least one task, and generates a response. The scheduling circuit of the exemplary system receives the at least one task and conducts a load balancing to select the at least one destination processing core. In an embodiment, the scheduling circuit further detects a critical sequences of tasks, schedules those tasks to be processed by a single destination processing core, and, upon completion of the critical sequence, conducts another load balancing to potentially select a different processing core to process more tasks.

Claims20

Dependent claims

A system comprising:

a plurality of processing cores, including at least one source processing core to generate at least one task and at least one destination processing core to receive and process the at least one task, and to generate a response;
and
a scheduling circuit comprising:
a task linked list to store received tasks;
a ready linked list to store tasks ready to be assigned to destination processing cores;
and
a scheduled linked list to store tasks that have been assigned to destination processing cores;
wherein the scheduling circuit to:
receive the at least one task, associate it with a flow identifier, store it in the task linked list to be processed, store it in the ready linked list to be scheduled, select the at least one destination processing core to process it, store it in the scheduled linked list to be transmitted, and transmit it to the at least one destination processing core;
and
wherein the at least one destination processing core is selected because of its relatively low load compared to other processing cores among the plurality of processing cores.

8 more elements

A non-transitory computer readable medium containing instructions that when executed, cause a plurality of processing cores and a scheduling circuit to perform a process comprising:

generating at least one task by at least one source processing core among the plurality of processing cores;
and
receiving the at least one task by the scheduling circuit, associating it with a flow identifier, storing it in a task linked list to be processed, storing it in a ready linked list to be scheduled, selecting at least one destination processing core to process it, storing it in the scheduled linked list to be transmitted, and transmitting it to the at least one destination processing core;
wherein the at least one destination processing core is selected because of its relatively low load compared to other processing cores among the plurality of processing cores.

1 more element

Dependencies are inferred from the claim text.

Work Conserving, Load Balancing, and Scheduling

Life of this patent

Work Conserving, Load Balancing, and Scheduling

Life of this patent

Abstract

Claims20