US 2017/0286151 A1 · Handling Memory Requests

Abstract

A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Claims20

Dependent claims

A module comprising:

an assignment module arranged to receive memory requests from a cache and to assign a transaction identifier to each received memory request, wherein the memory requests received from the cache include one or more memory addresses defined in a virtual address space;
a transaction tracker module arranged to receive a memory request from the assignment module with the assigned transaction identifier, to track the status of the memory request and to receive translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in the memory request to a physical memory address or a pointer to the translation;
and
an arbiter module arranged to receive a memory request from the transaction tracker module with the assigned transaction identifier when the memory request is ready for issue and to issue the memory request to a memory via an external bus and to trigger the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information.

1 more element

A method comprising:

receiving memory requests from a cache at a converter module;
assigning, in the converter module, a transaction identifier to each received memory request, wherein the memory requests received from the cache include one or more memory addresses defined in a virtual address space;
tracking, in the converter module, the status of the memory requests;
receiving, in the converter module, translation information from a memory management unit, wherein the translation information comprises a translation of a virtual memory address in one of the memory requests to a physical memory address or a pointer to the translation;
issuing said one of the memory requests from the converter module to a memory via an external bus, wherein the memory request issued to memory includes one or more physical memory addresses determined using the translation information;
and
triggering the freeing of the assigned transaction identifier in response to receiving a response from the memory via the external bus.

4 more elements

Dependencies are inferred from the claim text.

Handling Memory Requests

Life of this patent

Handling Memory Requests

Life of this patent

Abstract

Claims20