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US 2017/0286122 A1Published application
Instruction, Circuits, and Logic for Graph Analytics Acceleration
AssigneeIntel Corporation
InventorsLisa K. Wu, Tae Jun Ham, Nadathur Rajagopalan Satish, Narayanan Sundaram
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Abstract
A processor includes a front end including circuitry to receive and decode an instruction. The instruction is to perform a graph analytic function and pass the instruction to a graph accelerator. The graph accelerator including circuitry to process graph vertices and graph edges as datatypes, execute the instruction, and pass results of the instruction to a memory subsystem of the processor.
Claims20
A processor, comprising:
- a front end including circuitry to:
- receive and decode an instruction, the instruction to perform a graph analytic function;
- and
- pass the instruction to a graph accelerator;
- a graph accelerator including circuitry to:
- process graph vertices and graph edges as datatypes;
- execute the instruction;
- pass results of the instruction to a memory subsystem of the processor.
5 more elements
An accelerator circuit, comprising circuitry to:
- execute an instruction, the instruction to perform a graph analytic function;
- and
- process graph vertices and graph edges as datatypes;
- and
- pass results of the instruction to a memory of a system.
2 more elements
A method, comprising:
- offloading execution of an instruction to a graph accelerator, the instruction to perform a graph analytic function;
- in the graph accelerator, processing graph vertices and graph edges as datatypes;
- and
- pass results of the instruction to a memory of a system.
1 more element
Dependencies are inferred from the claim text.