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AssigneeIntel Corporation
InventorsJames A. Coleman, Philip C. Arellano, Garrett Drown
Estimating the term…
A processor of an aspect includes a plurality of caches at a plurality of different cache levels. The processor also includes a decode unit to decode a fetch instruction. The fetch instruction is to indicate address information for a memory location, and the fetch instruction is to indicate a cache level of the plurality of different cache levels. The processor also includes a cache controller coupled with the decode unit, and coupled with a cache at the indicated cache level. The cache controller, in response to the fetch instruction, is to store data associated with the memory location in the cache, wherein the fetch instruction is architecturally guaranteed to be completed. Other processors, methods, systems, and machine-readable storage mediums storing instructions are disclosed.
A processor comprising:
A method performed by a processor comprising:
A system to process instructions comprising:
The system of claim 23, wherein the fetch instruction is to indicate an amount of the data.
An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a fetch instruction, the fetch instruction to indicate address information for a memory location, and the fetch instruction to indicate a cache level as being any one of a plurality of different cache levels, the fetch instruction if executed by a machine is to cause the machine to perform operations comprising:
Dependencies are inferred from the claim text.