Instruction and Logic for Configurable Arithmetic Logic Unit Pipeline

A method, comprising:

• setting a mode field of a performance register associated with an arithmetic logic unit;
• decoding an instruction for the arithmetic logic unit;
• selecting between a normal computation corresponding to a normal result and an accelerated computation corresponding to an accelerated result based on the mode field of the performance register, wherein the accelerated computation is faster than the normal computation;
• performing the selected computation;
• and
• selecting between the normal result and the accelerated result based on the mode field of the performance register.

An arithmetic logic unit, comprising circuitry to:

• receive a decoded instruction;
• select between a normal computation corresponding to a normal result and an accelerated computation corresponding to an accelerated result based on a mode field of a performance register, wherein the accelerated computation is faster than the normal computation;
• perform the selected computation;
• and
• select between the normal result and the accelerated result based on the mode field of the performance register.