Processors, methods, and systems to allocate load and store buffers based on instruction type

A method performed by a processor, the method comprising:

• receiving memory access instructions of a first type;
• receiving memory access instructions of a second type;
• and
• allocating load buffer entries of a load buffer and store buffer entries of a store buffer for memory access operations based at least in part on whether the memory access operations correspond to the memory access instructions of the first type or the second type.

A computer system comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor to receive memory access instructions of a first type and memory access instructions of a second type, the processor comprising:
• a load store queue including:
• a load buffer that is to have a plurality of load buffer entries;
• a store buffer that is to have a plurality of store buffer entries;
• and
• wherein the load store queue is to allocate load and store buffer entries for memory access operations based at least in part on whether the memory access operations correspond to the memory access instructions of the first type or the second type;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.