Processors, methods, systems, and instructions to atomically store to memory data wider than a natively supported data width

A method performed by a processor comprising:

• receiving an atomic store to memory instruction at a given logical processor of the processor, the atomic store to memory instruction indicating data that is wider in bits than a widest data register that instructions of an instruction set of the given logical processor are able to specify, and the atomic store to memory instruction indicating memory address information associated with a memory location;
• and
• atomically storing the indicated data to the memory location, in response to the atomic store to memory instruction.

A processor comprising:

• a decode unit corresponding to a given logical processor, the decode unit to decode an atomic store to memory instruction, the atomic store to memory instruction to indicate data, and the atomic store to memory instruction to indicate memory address information associated with a memory location;
• and
• an execution unit coupled with the decode unit, the execution unit, in response to the atomic store to memory instruction, to atomically store the indicated data to the memory location, wherein a width in bits of the data that is to be atomically stored in response to the atomic store to memory instruction is to be wider than a width in bits of data to be atomically loaded by any instruction the decoder is able to decode.