Instruction, Circuits, and Logic for Data Capture for Software Monitoring and Debugging

A system, comprising:

• a processor;
• a front end including circuitry to receive an instruction to monitor execution of a thread;
• a decoder including circuitry to decode the instruction;
• a scheduler including circuitry to schedule the instruction;
• a retirement unit including circuitry to retire the instruction;
• and
• a core including circuitry to, based on execution of the instruction:
• monitor execution of the thread;
• identify an attempted read of an address during execution of the thread;
• determine whether a value at the address was previously read during monitoring of the execution of the thread;
• log the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread;
• and
• omit logging of the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread.

A method, comprising:

• receiving an instruction to monitor execution of a thread;
• decoding the instruction;
• scheduling the instruction;
• retiring the instruction;
• and
• based on execution of the instruction:
• monitoring execution of the thread;
• identifying an attempted read of an address during execution of the thread;
• determining whether a value at the address was previously read during monitoring of the execution of the thread;
• logging the attempted read based on a determination that the value at the address was previously read during monitoring of the execution of the thread;
• and
• omitting logging of the attempted read based on a determination that the value at the address was not previously read during monitoring of the execution of the thread.