Auxiliary Cache for Reducing Instruction Fetch and Decode Bandwidth Requirements

A method, comprising:

• receiving, by an auxiliary cache in a processor, a request from a binary translator to write auxiliary information for an instruction in an instruction stream to the auxiliary cache;
• storing the auxiliary information to the auxiliary cache;
• receiving the instruction;
• decoding the instruction;
• executing the instruction, including:
• accessing the auxiliary information stored in the auxiliary cache;
• blending the auxiliary information with the decoded instruction to produce a blended instruction;
• and
• providing the blended instruction to an execution unit for execution;
• and
• retiring the instruction.

A system, comprising:

• a binary translator;
• and
• a processor, including:
• a front end including circuitry to decode an instruction in an instruction stream;
• an execution unit including circuitry to execute the instruction;
• an auxiliary cache including circuitry to store auxiliary information for the instruction;
• an instruction blender;
• and
• a retirement unit including circuitry to retire the instruction;
• wherein:
• the auxiliary information is not decoded by the front end;
• the auxiliary cache comprises circuitry to:
• receive a request from the binary translator to write the auxiliary information to the auxiliary cache;
• store the auxiliary information in the auxiliary cache;
• and
• provide the auxiliary information to the instruction blender prior to execution of the instruction;
• the instruction blender comprises circuitry to:
• receive, from the auxiliary cache prior to execution of the instruction, the auxiliary information for the instruction;
• blend the decoded instruction with the auxiliary information to produce a blended instruction;
• and
• provide the blended instruction to the execution unit for execution.