Processor Core, Processor And Method For Executing A Composite Scalar-Vector Very Lare Instruction Word (VLIW) Instruction

2:

• The processor core of claim 1, wherein the composite VLIW instruction comprises a scalar atom and a vector atom.

3:

• The processor core of claim 1, wherein the composite VLIW instruction execution unit comprises a detector which determines whether a REPEAT field of the composite VLIW instruction is REP=1 or REP>1, and
• wherein if the detector determines that the REPEAT field in the composite VLIW instruction is REP=1, then the composite VLIW instruction execution unit executes each atom in the composite VLIW instruction at a single iteration.

4:

• The processor core of claim 3, wherein the composite VLIW instruction execution unit further comprises a composite VLIW instruction execution subunit, and if the detector determines that the REPEAT field in the composite VLIW instruction is REP>1, then the composite VLIW instruction execution subunit executes scalar atoms of the decoded composite VLIW instruction at a single iteration.

5:

• The processor core of claim 4, wherein if the detector determines that the REPEAT field in the composite VLIW instruction is REP>1, then the composite VLIW instruction execution subunit executes vector atoms of the decoded composite VLIW instruction during all REP iterations.

6:

• The processor core of claim 5, wherein if the detector determines that the REPEAT field in the composite VLIW instruction is REP>1, then the composite VLIW instruction execution subunit executes branch and control atoms of the decoded composite VLIW instruction at a single iteration.

7:

• The processor core of claim 6, wherein the single iteration at which the composite VLIW instruction execution subunit executes branch and control atoms of the decoded composite VLIW instruction comprises the last iteration.

8:

• The processor core of claim 4, wherein the single iteration at which the composite VLIW instruction execution subunit executes scalar atoms of the decoded composite VLIW instruction comprises the first iteration.

9:

• The processor core of claim 6, wherein the branch and control atoms of the decoded composite VLIW instruction comprise a field indicating the iteration at which the composite VLIW instruction execution subunit executes the branch and control atoms.

10:

• The processor core of claim 4, wherein the scalar atoms of the decoded composite VLIW instruction comprise a field indicating the iteration at which the composite VLIW instruction execution subunit executes the scalar atoms.

12:

• A processor comprising the processor core of claim 1.

15:

• The method of claim 14, further comprising:
• if the REPEAT field in the composite VLIW instruction is determined to be REP>1, then executing scalar atoms of the decoded composite VLIW instruction at a single iteration.

16:

• The method of claim 15, further comprising:
• if the REPEAT field in the composite VLIW instruction is determined to be REP>1, then executing vector atoms of the decoded composite VLIW instruction during all REP iterations.

17:

• The method of claim 16, further comprising:
• if the REPEAT field in the composite VLIW instruction is determined to be REP>1, then executing branch and control atoms of the decoded composite VLIW instruction at a single iteration.

20:

• A programmable storage medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform the method of executing a very large instruction word (VLIW) instruction of claim 13.