Memory Controller For Micro-Threaded Memory Operations

A memory controller to control a memory device, the memory device having a plurality of bank groups, the memory controller comprising:

• circuitry to provide a clock signal to the memory device, the clock signal having clock transitions;
• a command interface to transmit, to the memory device, row activation commands to instruct row activations and column access commands to instruct column accesses;
• and
• circuitry to schedule issuance of the row activation commands and the column access commands from the command interface, such that
• a first interval, defined by a first number of clock transitions to transpire between back-to-back row activations to banks within a common bank group, is longer than a second interval, defined by a second number of clock transitions to transpire between back-to-back row activations to banks within different bank groups, and
• a third interval, defined by a third number of clock transitions to transpire between back-to-back column accesses to banks within a common bank group, is longer than a fourth interval, defined by a fourth number of clock transitions to transpire between back-to-back column accesses to banks within different bank groups.

A memory controller to control a memory device, the memory device having a plurality of bank groups, the memory controller comprising:

• circuitry to provide a clock signal to the memory device, the clock signal having clock transitions;
• a command interface to transmit row activation commands and column access commands to the memory device, via a command bus;
• a data interface to exchange data with the memory device in association with each column access command;
• and
• circuitry coupled to the command interface to schedule issuance of the row activation commands and the column access commands to banks within the plurality of bank groups, such that
• a first interval, defined by a first number of clock transitions to transpire between back-to-back row activations to banks within a common one of the bank groups, is longer than a second interval, defined by a second number of clock transitions to transpire between back-to-back row activations to banks within different ones of the bank groups, and
• a third interval, defined by a third number of clock transitions to transpire between back-to-back column accesses to banks within a common one of the bank groups, is longer than a fourth interval, defined by a fourth number of clock transitions to transpire between back-to-back column accesses to banks within different ones of the bank groups;
• wherein the memory controller is to transmit bank address information as part of each command of the row activation commands and column access commands, to communicate selection of a bank group of the plurality of bank groups, and to communicate selection of a bank within the selected bank group.

A method of operation in a memory controller, the memory controller to control a memory device, the memory device having a plurality of bank groups, the method comprising:

• providing a clock signal to the memory device, the clock signal having clock transitions;
• transmitting to the memory device, via a command interface, row activation commands to instruct row activations and column access commands to instruct column accesses;
• and
• scheduling issuance of the row activation commands and the column access commands from the command interface, such that
• a first interval, defined by a first number of clock transitions to transpire between back-to-back row activations to banks within a common bank group, is longer than a second interval, defined by a second number of clock transitions to transpire between back-to-back row activations to banks within different bank groups, and
• a third interval, defined by a third number of clock transitions to transpire between back-to-back column accesses to banks within a common bank group, is longer than a fourth interval, defined by a fourth number of clock transitions to transpire between back-to-back column accesses to banks within different bank groups.